Transcript · STATIC TIMING ANALYSIS | SETUPP | HOLD | SYNOPSYS | PRIMETIME | PHYSICAL DESIGN | VLSIFaB · HOLD ANALYSIS | STA - 5 | Static Timing ... ... <看更多>
「primetime sta」的推薦目錄:
- 關於primetime sta 在 [問題] 不懂Primetime的set min/max delay.. - 看板Electronics 的評價
- 關於primetime sta 在 Timing Analysis using Prime Time - YouTube 的評價
- 關於primetime sta 在 2018/03/30 STA Virtual Clock - Leon Sun 的評價
- 關於primetime sta 在 sta_basics_course/sta_basics_course.rst at master - GitHub 的評價
- 關於primetime sta 在 PRIMETIME HEADLINE I BAGONG HALAL NA MAYOR NG ... 的評價
- 關於primetime sta 在 verilog - sdf generation using prime time 的評價
primetime sta 在 2018/03/30 STA Virtual Clock - Leon Sun 的推薦與評價
2017/11/22 STA Debug PrimeTime Crash Issue In A Restored Session. 之前一直用的是2015版本的PrimeTime,最近项目中有path margin约束,需要更新 ... ... <看更多>
primetime sta 在 sta_basics_course/sta_basics_course.rst at master - GitHub 的推薦與評價
PrimeTime Hands-on. STA Session; PT Exercise 1: Simple FF-to-FF Path; PT Exercise 2: Effect of Negedge Clocking; PT Exercise 3: Simple FF-to-FF Path with ... ... <看更多>
primetime sta 在 PRIMETIME HEADLINE I BAGONG HALAL NA MAYOR NG ... 的推薦與評價
NG STA.MAGDALENA SORSOGON, NAG PAABOT NG PASASALAMAT SA LAHAT NG SUMUPORTA SA SAKANYANG KANDIDATURA. Ang detalye sa ulat ni ... ... <看更多>
primetime sta 在 verilog - sdf generation using prime time 的推薦與評價
Even more sophisticated Static Timing Analysis (STA) can be performed using Synopsys Primetime. You can refer to Synopsys documentations and ... ... <看更多>
primetime sta 在 [問題] 不懂Primetime的set min/max delay.. - 看板Electronics 的推薦與評價
不好意思,最近才開始接觸這些EDA工具
對於 Primetime的 set_max/min_delay 不太瞭解
User guide上面是說:
"By default, PrimeTime calculates the maximum and minimum path delays
by considering the clock edge times. To override the default maximum or
minimum time with your own specific time value, use the set_max_delay or
set_min_delay command."
然後舉了個例子:
set_max_delay 12 -from [get_cells REGA] -to [get_cells REGB]
With this timing exception, PrimeTime ignores the clock relationships.
A path delay between these registers that exceeds 12 time units minus
the setup requirement of the endpoint register is reported as a
timing violation.
我不懂的是標記起來的這句,就我的理解 set_max/min_delay 就是把這個path的
max/min delay當成使用者設定的這個數值來看(不管真實狀況如何)
既然tool已經把delay定死成這個數值了,又怎麼會有violation呢?
還是說如果這條path的真實max delay超過12,他還是會當成12來看
只是最後報出violation給我們呢?
謝謝 ^^
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